Internet eXchange Architecture Notes

Internet eXchange Architecture Notes
IXP1200 小記

ENP2505_DataSheet.pdf

Meetings
Environment (GettingStarted.pdf)
- Hardware Configuration
- Software Configuration
- [Top]

Hardware (IXP1200 HW Ref Manual.pdf)

IXP1200 Block Diagram

Block Notes

Internal Buses 200 Mhz	StrongARM (ARM = Advanced Reduced Instruction Set Computer (RISC) Machine)	232 MHz
	6 Microengines (4 non-preemptive Threads in round-robin order for each, RISC)	232 MHz
	SDRAM (256MB, 64-bit data path)	116 MHz
	SRAM (8MB, 32-bit data path)	116 MHz
	IX Bus Interface (RFIFO, TFIFO)	104 MHz
	PCI Bus	66 MHz

PS: StronARM core and six microengines are all on the same die.

The Properties of the Three IXP12xx Memory Interfaces

Memory Interface	Minimum Addressable Unit (bytes)	Size (bytes)	Approx. Unloaded Latency (clks)	Sepcial Operations
Scratchpad	4	4K (on chip)	12 - 14	Atomic increment, bit test-and-set, bit test-and-clear
SRAM	4	8M (addressable)	16 - 20	Content Addressable Memory (CAM) lock, bit tes-and-set, bit test-and-clear, push-pop queues
SDRAM	8	256M (addressable)	33 - 40	Direct path to and from the FBI which allows data to be moved between the two without first going through one of the processors.

Microengine Transfer Registers and internal data paths
Data can be moved simultaneously
- SDRAM <=> Microengines or IX Bus
- SRAM <=> Microengines
- SRAM <=> PCI
- IX Bus <=> Microengines
Another Diagram from IEEE Network July/Augest 2003
Citing from IEEE Journal
- Closely examining the hardware architecture of IXP1200 shown in Figure helps to elucidate our DiffServ implementation. The 32-bit 200 MHz StrongARM core governs the initialization of the whole system and part of the packet processing. A memory management unit is also included to translate virtual addresses into physical addresses and control memory access permission.
- The six 200 MHz microengines, supporting four hardware contexts (i.e., threads), are primarily used to receive, manipulate, and transmit packets. For networking purposes, microengines also support zero context switching overhead, single-cycle ALU with shifter, and other specifically designed instructions for bit, byte, and longword operations.
  也就是說，microengines的主要功用是接收，處理，以及傳送封包。
- The SRAM is used to store lookup tables and pointers in scheduling queues for packet forwarding, while the SDRAM is used to store mass data of packets. The 64-bit IX bus interface unit is responsible for servicing medium access control (MAC) interface ports on the IX bus, and moving data to and from the receive and transmit first-in first-out buffers (FIFOs). It provides a 4.2 Gb/s (64 bits at 66 MHz) interface to MAC devices, meaning that it can afford 2.1 Gb/s of the input ports and 2.1 Gb/s of the output ports. In addition, two IXP1200 network processors can be directly supported on the IX bus without additional support logic.
  也就是說，SRAM主要用來儲存lookup tables和pointers，而SDRAM主要用來儲存封包的大量資料。
- The operations of IXP1200 hardware components when handling packet forwarding services are described below. At boot time, the StrongARM loads the boot image from boot ROM or via serial/Ethernet connection, and initializes other functional units, including loading the routing table into SRAM and microcode into microengines. The system is now ready to receive packets. When the ready bus sequencer detects an incoming packet in a MAC, it notifies the corresponding receiver thread to retrieve and store the packet in the receive FIFO (RFIFO). After completing the routing table lookup, the receiver thread moves the packet to SDRAM in order to wait to be forwarded. A transmitter thread of another microengine later forwards the packet in SDRAM through the transmit FIFO (TFIFO) to another MAC. Multiple receiver, transmitter, and scheduler threads may be distributed to six microengines, although some restrictions apply.
  也就是說，開啟的時候StrongARM會把boot image從boot ROM載入，然後初始話其他unit：載入routing table進入SRAM，載入microcode進入microengines。在一切就緒後，開始接收傳送封包：packets => MAC =告知receiver thread去處理並把它存在RFIFO> RFIFO =完成routing table lookup後> SDRAM =另外的microengine的transmitter thread把packet導入TFIFO> TFIFO => => another MAC。
StrongARM Block Diagram

StrongARM Core Internal Connections

Unit	Resource
PCI Unit	Full access to the PCI Bus, including all PCI bus transactions. Full access to PCI Unit registers. Separate, shared 32-bit bus between the StrongARM core (ATU) data bus and the PCI Unit.
SDRAM Unit	Full access to SDRAM.
SRAM Unit	Full access to SRAM, including Flash and other devices hooked up to the SRAM Bus.
IX Bus Unit	Access to Control and Status registers within the IX Bus Unit. Access to Scratchpad RAM within the IX Bus Unit. No access to the Receive or Transmit FIFOs or the IX data bus.
Microengines	Access to Microengines' Program Control Store to program the Microengines. Access to Control and Status Registers, including PC (Program Counter). No access to Microengine Transfer Registers.

Microengine internal structure

Microengines have 3 different types of registers:

Register Type	Explanation
General purpose	Each microengine has 128, 32-bit general purpose registers (GPRs), allocated into two banks of 64 registers (A and B banks). In thread-local mode, each thread accesses a unique set of 32 GPRs, or 16 A bank GPRs and 16 B GPRs. In absolute mode, GPRs registers are accessible by any thread. Absolute registers are useful for inter-thread communication within a microengine.
SRAM transfer	Each Microengine has 64 SRAM transfer registers divided equally into read-only and write-only. SRAM transfer registers are used to read from and write to all functional units on the IXP12xx except for the SDRAM unit. When data is read from other functional units, it its placed in SRAM transfer registers, and when microengine code writes data to these units, it must firest be placed in transfer registers.
SDRAM transfer	Each microengine has 64 SDRAM transfer registers divided equally into read-only and write-only. SDRAM transfer registers are used exclusively for communication between the microengines and the SDRAM unit.

Microengine Internal Connections

Unit	Resource
StrongARM Core	The Microengines may interrupt the StrongARM core. The StrongARM core can read aregister to determine which Microengine generated the interrupt. No other access to StrongARM Core.
PCI Unit	No access to the PCI Bus. Access only to the Control and Status Registers for the two DMA Controllers in the PCI Unit. By programming these registers, the Microengines may initiate DMA transfers between a block of SDRAM memory and a PCI device.
SDRAM Unit	Full access to SDRAM.
SRAM Unit	Full access to SRAM, including Flash and other devices hooked up to the SRAM Bus.
IX Bus Unit	Full access to the IX Bus Unit, including the Scratchpad RAM, Hardware Hashing Unit, Receive and Transmit FIFOs, Ready Bus, and Control and Status Registers.
Microengines	Each Microengine has access to its Program Control Store so it can execute instructions. The Microengines do not have read or write access to the Control Store (they cannot read or write their own Control Store, only the StrongARM core can do that). Inter-thread signalling between Microengine threads is provided. Each Microengine is self-contained, so one Microengine cannot access the Control Store, or Registers of another Microengine.

SRAM Unit external interfaces and SRAM Unit Block Diagram

SRAM Unit Internal Connections

Unit	Resource
StrongARM Core	Full access.
PCI Unit	No connection between the SRAM Unit and the PCI Unit.
SDRAM Unit	No connection between the SRAM Unit and the SDRAM Unit.
IX Bus Unit	No connection between the SRAM Unit and the IX Bus Unit.
Microengines	Full access.

SDRAM Unit Block Diagram

SDRAM Unit Internal Connections

Unit	Resource
StrongARM Core	Full access.
PCI Unit	There is a separate, and unshared 32-bit bus connecting the SDRAM Unit and the PCI Bus Unit. This allows devices on the PCI Bus better access to data buffers within the SDRAM Unit. The two DMA Controllers in the PCI Unit have access to SDRAM data.
SRAM Unit	No connection between the SRAM Unit and the SRAM Unit.
IX Bus Unit	There is a 32-bit bus connecting the SDRAM Unit and the IX-Bus Unit’s Receive and Transmit FIFOs.
Microengines	Full access.

PCI Unit Block Diagram

PCI Unit Internal Connections

Unit	Resource
StrongARM Core	Full access. The StrongARM core can access any devices on the PCI Bus. The StrongARM core can program any of the PCI Unit’s Control and Status Registers.
SDRAM Unit	Unshared, direct 32-bit bus connecting SDRAM Unit and the PCI Unit. Devices on the PCI Bus have access to SDRAM. DMA Controllers within the PCI Unit can transfer data between SDRAM and devices on the PCI Bus.
SRAM Unit	No connection between the SRAM Unit and the PCI Unit. Devices on the PCI Bus cannot access SRAM. DMA Controllers within the PCI Unit cannot access SRAM.
IX Bus Unit	No connection between the IX Bus Unit and the PCI Unit. Data that needs to be transferred between the IX Bus (Transmit and Receive FIFOs) and the PCI Bus must be transferred by the Microengines (by way of their Transfer Registers).
Microengines	The Microengines can only access the Control and Status Registers for the DMA Controllers within the IX Bus Unit. No other access. The Microengines cannot access devices on the PCI Bus (and vice versa).

IX Bus Unit Block Diagram
IX Bus data flow

PCI Unit Internal Connections

Unit	Resource
StrongARM Core	Limited Access. The StrongARM core can access the Scratchpad RAM within the IX Bus Unit, as well as a number of Control and Status Registers within the IX Bus Unit. The StrongARM Core cannot access the Receive and Transmit FIFOs within the IX Bus Unit. The StrongARM Core can program the Ready Bus Controller within the IX Bus Unit.
SDRAM Unit	Two direct, unshared, independent busses connect the SDRAM Unit with the IX Bus Unit. The SDRAM read bus is connected to the Receive FIFO, while the write bus is connected to the Transmit FIFO.
SRAM Unit	No connection between the SRAM Unit and the IX Bus Unit’s FIFOs. Data that needs to be transferred between the IX Bus (Transmit and Receive FIFOs) and SRAM must be transferred by the Microengines (by way of their Transfer Registers).
PCI Unit	No connection between the IX Bus Unit and the PCI Unit. Data that needs to be transferred between the IX Bus (Transmit and Receive FIFOs) and the PCI Bus must be transferred by the Microengines (by way of their Transfer Registers).
Microengines	Full Access, including access to the Scratchpad RAM, the Hashing Unit, programming the Ready Bus Controller, the Receive and Transmit FIFOs, and all Control and Status Registers.

[Top]

Setup (SDK_Install.pdf)

Configuring ROM based components
爛肉已經做過，所以沒做過。

Configuring the Linux Host

Install RedHat 7.2 (筆記註：不知道能不能用Fedora？)

Create 3 partitions (筆記註：只分/(ext3)和swap其實也可以。)

Mount Point	Filesystem Type	Size (MB)	Additional Size Options
/boot	ext2	128	Fixed size
	swap	512	Fixed size
/	ext2		Fill to maximum allowable size

Boot Loader: GRUB (筆記註：不一定要on MBR。)
No firewall.
Add ixa user account. (筆記註：感覺好像不需要。)
Package Selection: NFS, Software Development, Kernel Development, Windows Compatibility/Interoperability
(Check tftp, dhcp.)

Upgrading the Host Linux Kernel

root login.
更新kernel.
rpm -recompile linux_24_17src.rpm
(ENP Linux SDK光碟/ENP_LINUX_SDK/HOST_LINUX_UPGRADE/LINUX_24_17SRC.RPM)

修改/etc/grub.conf

default=1
title RedHat Linux (2.4.7)
  root (hd0, 0)
  kernel vmlinuz-2.4.7-10 ro root=/dev/hda0
  initrd /initrd-2.4.7-10.img
title RedHat Linux (2.4.17)
  root (hd0, 0)
  kernel vmlinuz-2.4.17-10 ro root=/dev/hda0
  initrd /initrd-2.4.7-10.img

設定tftp開機service。vi /etc/xinetd.d/tftp

service tftp
{
  socket_type  = dgram
  protocol  = udp
  wait    = wait
  user    = nobody
  log_on_success  += USERID
  log_on_failure  += USERID
  server    = /usr/sbin/in.tftpd
  server_args  = /tftpboot -l
  disabled  = no
}

新的kernel沒有支援intel以外的網卡，也沒有iptables，所以要重新將網卡和iptables的module安裝起來需要重新編譯核心：

cd /usr/src/linux-2.4.17
make menuconfig (or make xconfig)
(Network devices -> Realtek RTL8139 or others...)
(Networking options -> Network packet filtering (replaces ipchains))
(Networking options -> IP: Netfilter Configuration -> IP tables support...)
(Networking options -> IP: Netfilter Configuration -> Connection tracking (required for masq/NAT))
(Networking options -> IP: Netfilter Configuration -> Full NAT -> MASQUERADE)
make dep
make clean
make bzImage
make modules
make modules_install
make install
(筆記註：龜毛的話再改一次/etc/grub.conf。)

reboot.

Install the Intel IXA SDK
- Installing the IXA SDK on the Linux Host
  - login root.
  - mount IXA SDK VOLII CD1
    rpm -ivh ixa.sdk-2.01.D-fcs.i386.rpm
    rpm -ivh ixa.executive-2.01.D-fcs.i386.rpm
    rpm -ivh armbe-v4b-fcs.i386.rpm
    rpm -ivh ixa.binaries-2.01.D-fcs.i386.rpm
    (rpm -ivh nfs-utils-0.3.1-13.i386.rpm)
  - 修改/etc/profile加入
```
# IXA SDK path settings
if ! echo $PATH | /bin/grep -q "/usr/local/armbe/bin" ; then
  PATH="$PATH:/usr/local/armbe/bin"
fi
if ! echo $PATH | /bin/grep -q "/opt/ixasdk/bin" ; then
  PATH="$PATH:/opt/ixasdk/bin"
fi

IXROOT="/opt/ixasdk"
CONFIG="ARM_BE"

export PATH USER LOGNAME MAIL HOSTNAME HISTSIZE INPUTRC IXROOT CONFIG
```
- Installing IXA SDK on the Windows Development Workstation
  - ENP Linux SDK光碟，下一步 -> 下一步 -> ...。
  - Cygwin記得選全裝(主要需要make, gcc)。
  - 解壓縮IXA_SDK_201A_PATCH.exe到C:\IXP1200。
    更新cygwin.bat複製到C:\eLinuxIDE-IXP1200\cygwin。
- 使用VMware須知：
  - VMware以NAT來與linux網路溝通。
  - 設定vmware-config.pl時vmnet8需設定為192.168.x.x。
  - 為了讓Workbench能與IXP1200 Embedded Linux溝通必須設定iptables如下：
```
echo 1 > /proc/sys/net/ipv4/ip_forward  // 開啟ip_forward
(或是修改/etc/sysctl.conf設定variable net.ipv4.ip_forward = 1)
/sbin/iptables -t nat -A POSTROUTING -o vmnet8 -s 192.168.0.2 -j MASQUERADE
      
```
ENP Configuration
- ENP Software Installation
  - rpm -recompile boot_drv_201_3src.rpm
    (ENP Linux SDK光碟/ENP_LINUX_SDK/ENP_2505_DRIVER/BOOT_DRV201_3SRC.RPM)
  - 這會安裝ENP-2505/6 drivers, ENP's embedded Linux(2.3.99), boot scripts程式到/opt/ixasdk/enp-2505。
- Rebuilding the ENP Linux kernel
  - ```
  cd /opt/ixasdk/enp2505/src/linuxIXAedu
  make menuconfig
  
  Select "System and processor types"
  Under "IXP Board type" select ENP-2505
  Select "Save and exit"
  
  make dep; make clean; make zImage
```
- This procedure will copy the zImage kernel into /tftpboot for the PCI download scripts.
- Applying the IXA SDK patch
  - ```
  cd /opt
  tar -zcvf ixasdk.tgz ixasdk
  cp /mnt/cdrom/ENP_UPDATES_FOR_IXA_SDK/enp_changes_ixa_sdk.path /opt
  cd /opt/ixasdk
  cat ../enp_changes_ixa_sdk.patch | patch -pl
```
- Rebuilding the pciDg dirver module
  - 編輯/opt/ixasdk/enp-2505/src/pciDg/rules.mk
```
ARM-TOOLS = /usr/local/armbe/bin/armv4b-unknown-linux-
ARM-KERNEL-INCLUDES = $(PWD)/../linuxIXAedu/include
X86-KERNEL-INCLUDES =
```
    或是ln -s /opt/ixasdk/enp-2505/src/linuxIXAedu /opt/ixasdk/enp-2505/src/linux
  - make clean; make
- Rebuilding the SDK
  - 編輯/opt/ixasdk/src/arch.incl把IX_TARGET_TYPE變數改為ENP2505。
  - Rebuilding the MicroAce framework
```
cd /opt/ixasdk/src/microace
make clean; make
```
ENP2505/6 Specific Configuration
- Installing the ENP-2505/6 IXP1200 PCI Board
- Booting the ENP-2505/6
```
cd /opt/ixasdk/enp-2505/bootixp
./bootixp
```
- Verifying ENP-2505/6 Driver operation
  - ** Finished ENP-2505 driver install **
  - lsmod
```
On ENP:
Module        Size Used by
pciDgNet-arm  2668  1
pciDg-arm     7544  0 [pciDgNet-arm]

On Linux:
Module        Size Used by
pciDgNet      1920  1
pciDg         5568  0 [pciDgNet]
```
- ping 192.168.0.4(Linux) 192.168.0.2(ENP)
  (IP可以在/opt/src/bootxixp/create_environment.rc修改。)
ENP-2505/6 NFS Filesystem - mount在/nfs

Completing the Host networking configuration(筆記註：同之前提到的VMware作法。)

echo 1 > /proc/sys/net/ipv4/ipforward

編輯/etc/sysctl.conf
variable net.ipv4.ip_forward = 1

-----VMWare Windows-----
iptables -t nat -A POSTROUTING -o vmnet8 -s 192.168.0.2 -j MASQUERADE
------------------------

[Top]

SDK
- Workbench Tutorial: IXP1200 Dev Tool UG.pdf
- Count Application Example Data Flow
- Microengine C RFC1812 Example Data Flow
- Flowchart of Mpacket Reassembly Followed by Packet Processing
- [Top]
Run (SDK_Tutorial.pdf) - Running simple count application
- Compiling the Microcode Source Files (Under Windows)
  - Using Makefile.win (first time)
    1. Open Cygwin.
    2. ```
    $IXROOT = /opt/ixasdk
    $CONFIG = ARM_BE
```
3. ```
cd $IXROOT/src/microace/aces/tutorial1/ucbuild
```
    4. ```
    make -f Makefile.win
```
5. ftp to linux:
```
    ftp> cd /opt/ixasdk/bin/arm-be
    ftp> mput *.uof
```
- Using IXP1200 Microengine Development Environment (debugging phase)
  1. Open Workbench.
  2. Open project $IXROOT\src\microace\projects\Count_8_1\Count_8_1.dwp.
  3. Build.
  4. Debug -> Hardware; Hardware -> Option -> Connect via Ethernet (Enter IXP1200's IP)
- Compiling the Core Component of the MicroACE (Under Linux)
  1. $IXROOT = /opt/ixasdk
    $CONFIG = ARM_BE
    $IXPSDKROOT = C:/ixp1200 (not needed?)
  2. ```
  cd $IXROOT/src/microace/aces/tutorial1/count_ace1
```
3. ```
(make clean;) make
```
  4. ```
  cd $IXROOT/src/microace/projects/Count_8_1
```
5. Edit ixsys_count_8_1.config.
  - mode 0: No workbench.
    mode 1: Download and debug via workbench.
  - ENP-2505: Port 0-3 10/100
    ENP-2506: Port 0-1 1000
    ENP-3511: Port 0-7 10/100
6. ```
(make clean;) make
```
    (This will export ixsys_count_8_1.config to the directory $IXROOT/bin/arm_be.)
- Starting and Running the Core Application (Under IXP1200 embedded Linux)
  1. ```
  cd /nfs/ixasdk/bin/arm-be
```
2. ```
./ixstart ixsys_count_8_1.config
```
  3. (If needed, Start Debugging at workbench side.)
Run2 (IXPCourse.pdf) - Running L3 forwarder application
- Compiling the Microcode Source Files (Under Windows)
  - Using Makefile.win (first time)
    1. Open Cygwin.
    2. ```
    $IXROOT = /opt/ixasdk
    $CONFIG = ARM_BE
```
3. ```
cd $IXROOT/src/microace/aces/tutorial1/ucbuild
```
    4. ```
    make -f Makefile.win
```
5. ftp to linux:
```
    ftp> cd /opt/ixasdk/bin/arm-be
    ftp> mput *.uof
```
- Compiling the Core Component of the MicroACE (Under Linux)
  1. $IXROOT = /opt/ixasdk
    $CONFIG = ARM_BE
    $IXPSDKROOT = C:/ixp1200 (not needed?)
  2. ```
  cd $IXROOT/src/microace/apps/l3config
```
3. ```
(make clean;) make
```
  4. ```
  cd $IXROOT/src/microace/aces/l3forward_ace
```
5. Edit ixsys.config-l3fwdr.
6. ```
(make clean;) make
```
    (This will export ixsys.config-l3fwdr to the directory $IXROOT/bin/arm_be.)
- Starting and Running the Core Application (Under IXP1200 embedded Linux)
  1. ```
  cd /nfs/ixasdk/bin/arm-be
```
2. ```
./ixstart ixsys.config-l3fwdr
```

Programming (IXP1200 Prog Ref Manual.pdf)

Data Terminology

Term	Bits
Byte	8
Word	16
Longword	32
Quadword	64

Microengine Data Paths

Register Name Form	Meaning
reg_name	Context-relative GPR
@reg_name	Absolute GPR
$reg_name	Context-relative SRAM XFER register
@$reg_name	Absolute SRAM XFER register
$$reg_name	Context-relative SDRAM XFER register
@$$reg_name	Absolute SDRAM XFER register

Conclusions:
Register names are strings of alpanumeric characters and underscores (_).
SRAM transfer registers have a single dollar sign ($) in front of them.
SDRAM transfer registers have two dollar signs ($$) in front of them.
Absolute registers of any of the three types add an at sign (@) in front.

Assembler Directives

Feature	Directive
Assembler Loops	#for #repeat #while #endloop
Assembler Macros	#macro #endm
Conditional Assembly	#ifdef #ifndef #if #else #elif #endif
Error Reporting	#error #warning
Export Function	.export_func
File Inclusion	#include
Function Table	.func_table
Import Variable	.import_var
Linker Directives	.image_name .entry .page .thread_type .ucode_size
Local Regions	.local .endlocal
Manual Register Specification	.areg .breg .$reg .$$reg
Operand Synonym	.operand_synonym
Structured Assembly	.if .elif .else .endif .repeat .until .while .endw .break .continue
Subroutine Definition	.subroutine .endsub
Token Replacement	#define #undef #define_eval
Transfer Order	.xfer_order .xfer_order_rd .xfer_order_wr
Segment	.segment
Virtual Set	.set

Microengine Instructions

Instruction	Description
Arithmetic, Rotate, and Shift Instructions
ALU	Perform an ALU operation.
ALU_SHF	Perform an ALU and shift operation.
DBL_SHF	Concatenate two longwords, shift the result, and save a longword.
Branch and Jump Instructions
BR, BR=0, BR!=0, BR>0, BR>=0, BR<0, BR<=0, BR=cout, BR!=cout	Branch on condition code.
BR_BSET, BR_BCLR	Branch on bit set or bit clear.
BR=BYTE, BR!=BYTE	Branch on byte equal.
BR=CTX, BR!=CTX	Branch on current context.
BR_INP_STATE	Branch on event state (e.g., SRAM done).
BR_!SIGNAL	Branch if signal deasserted.
JUMP	Jump to label.
RTN	Return from a branch or a jump.
Reference Instructions
CSR	CSR reference.
FAST_WR	Write immediate data to the thd_ done CSRs.
LOCAL_CSR_RD, LOCAL_CSR_WR	Read and write CSRs.
R_FIFO_RD	Read the receive FIFO.
PCI_DMA	Issue a request to the PCI Unit.
SCRATCH	Scratchpad reference.
SDRAM	SDRAM reference.
SDRAM_CRC	SDRAM CRC reference. (IXP1240 and IXP1250 only)
SRAM	SRAM reference.
T_FIFO_WR	Write to the transmit FIFO.
Local Register Instructions
FIND_BSET, FIND_BSET_WITH_MASK	Determine position number of first bit set in an arbitrary 16-bit field of a register.
IMMED	Load immediate word and sign extend or zero fill with shift.
IMMED_BO, IMMED_B1, IMMED_B2, IMMED_B3	Load immediate byte to a field.
IMMED_WO, IMMED_W1	Load immediate word to a field.
LD_FIELD, LD_FIELD_W_CLR	Load byte(s) into specified field(s).
LOAD_ADDR	Load instruction address.
LOAD_BSET_RESULT1, LOAD_BSET_RESULT2	Load the result of a find_bset or find_bset_with_mask instruction.
Miscellaneous Instructions
CTX_ARB	Perform context swap and wake on event.
NOP	Perform no operation.
HASH1_48, HASH2_48, HASH3_48	Perform 48-bit hash.
HASH1_64, HASH2_64, HASH3_64	Perform 64-bit hash.

traceASM
[Top]

ACE (MicroACE_Design.pdf.pdf)

Experiences

Date	Experiences
2004/03/01	Y. K. Chuang: "我們做資訊的，不可能把所有東西都搞懂之後才動工... 跳進去發現問題再出來，直接實作發現問題之後再來找答案會比較實在。"
2004/03/02	蘇文鈺: "學習任何一種組語最先要做同時也最重要的是把硬體架構搞懂。"
2004/03/09	jasonmel: 多看圖案，看不懂再看文字，可以大幅提升閱讀速度也大幅減少看文字的發呆次數。另外邊看邊做筆記效果也比較好。
2004/07/04	jasonmel: 實際操作一次勝過光看文字十遍。

[Top]

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